ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7880ACPZ-RL
(Rev.:RevA)

Polyphase Multifunction Energy Metering IC with Harmonic Monitoring

Analog Devices 

Data Sheet

THEORY OF OPERATION

ANALOG INPUTS

The ADE7880 has seven analog inputs forming current and

voltage channels. The current channels consist of four pairs of

fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP

and ICN, and INP and INN. These voltage input pairs have a

maximum differential signal of ±0.5 V.

The maximum signal level on analog inputs for the IxP/IxN

pair is also ±0.5 V with respect to AGND. The maximum

common-mode signal allowed on the inputs is ±25 mV. Figure 35

presents a schematic of the input for the current channels and

their relation to the maximum common-mode voltage.

V1 + V2

DIFFERENTIAL INPUT

V1 + V2 = 500mV MAX PEAK

COMMON MODE

VCM = ±25mV MAX

+500mV

VCM

–500mV

IAP, IBP,

V1 ICP, OR INP

VCM

V2 IAN, IBN,

ICN, OR INN

Figure 35. Maximum Input Level, Current Channels, Gain = 1

All inputs have a programmable gain amplifier (PGA) with a

possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and

IC inputs is set in Bits[2:0] (PGA1[2:0]) of the Gain register.

The gain of the IN input is set in Bits[5:3] (PGA2[2:0]) of the

Gain register; thus, a different gain from the IA, IB, or IC inputs

is possible. See Table 43for details on the Gain register.

The voltage channel has three single-ended voltage inputs: VAP,

VBP, and VCP. These single-ended voltage inputs have a maximum

input voltage of ±0.5 V with respect to VN. The maximum

signal level on analog inputs for VxP and VN is also ±0.5 V

with respect to AGND. The maximum common-mode signal

allowed on the inputs is ±25 mV. Figure 36 presents a schematic

of the voltage channels inputs and their relation to the maximum

common-mode voltage.

GAIN

SELECTION

IxP, VyP

VIN

IxN, VN

K × VIN

NOTES

1. x = A, B, C, N

y = A, B, C.

Figure 36. Maximum Input Level, Voltage Channels, Gain = 1

All inputs have a programmable gain with a possible gain

selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]

(PGA3[2:0]) in the Gain register (see Table 43).

Figure 37 shows how the gain selection from the Gain register

works in both current and voltage channels.

ADE7880

V1

+500mV

VCM

–500mV

DIFFERENTIAL INPUT

V1 + V2 = 500mV MAX PEAK

COMMON MODE

VCM = ±25mV MAX

VAP, VBP,

V1 OR VCP

VCM

VN

Figure 37. PGA in Current and Voltage Channels

ANALOG-TO-DIGITAL CONVERSION

The ADE7880 has seven sigma-delta (Σ-Δ) analog-to-digital

converters (ADCs). In PSM0 mode, all ADCs are active. In

PSM1 mode, only the ADCs that measure the Phase A, Phase B,

and Phase C currents are active. The ADCs that measure the

neutral current and the A, B, and C phase voltages are turned

off. In PSM2 and PSM3 modes, the ADCs are powered down to

minimize power consumption.

For simplicity, the block diagram in Figure 38 shows a first-

order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator

and the digital low-pass filter.

ANALOG

LOW-PASS FILTER

R

C

CLKIN/16

INTEGRATOR

LATCHED

+

–

+ COMPARATOR

–

VREF

DIGITAL

LOW-PASS

FILTER

24

.....10100101.....

1-BIT DAC

Figure 38. First-Order Σ-∆ ADC

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7880, the sampling clock is equal to 1.024 MHz

(CLKIN/16). The 1-bit DAC in the feedback loop is driven by

the serial data stream. The DAC output is subtracted from the

input signal. If the loop gain is high enough, the average value

of the DAC output (and, therefore, the bit stream) can approach

that of the input signal level. For any given input value in a

single sampling interval, the data from the 1-bit ADC is

virtually meaningless. Only when a large number of samples are

averaged is a meaningful result obtained. This averaging is

carried out in the second part of the ADC, the digital low-pass

filter. By averaging a large number of bits from the modulator,

the low-pass filter can produce 24-bit data-words that are

proportional to the input signal level.

Rev. A | Page 25 of 104

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