ADE7880ACPZ-RL(RevA) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADE7880ACPZ-RL
(Rev.:RevA)

Polyphase Multifunction Energy Metering IC with Harmonic Monitoring

Analog Devices 

ADE7880

Data Sheet

Table 16 presents the settling time for the fundamental reactive

power measurement, which is the time it takes the power to

reflect the value at the input of the ADE7880.

Table 16. Settling Time for Fundamental Reactive Power

Input Signals

63% PMAX

100% PMAX

375 ms

875 ms

Fundamental Reactive Power Gain Calibration

The average fundamental reactive power from the LPF output in

each phase can be scaled by ±100% by writing to one of the phase’s

VAR gain 24-bit register (APGAIN, BPGAIN, or CPGAIN). Note

that these registers are the same gain registers used to

compensate the other powers computed by the ADE7880. See

the Active Power Gain Calibration section for details on these

registers.

Fundamental Reactive Power Offset Calibration

The ADE7880 provides a fundamental reactive power offset

register on each phase. The AFVAROS, BFVAROS, and CFVAROS

registers compensate the offsets in the fundamental reactive

power calculations. These are signed twos complement, 24-bit

registers that are used to remove offsets in the fundamental

reactive power calculations. An offset can exist in the power

calculation due to crosstalk between channels on the PCB or in

the chip itself. The resolution of the registers is the same as for

the active power offset registers (see the Active Power Offset

Calibration section).

As stated in the Current Waveform Gain Registers section, the

serial ports of the ADE7880 work on 32-, 16-, or 8-bit words

and the DSP works on 28 bits. Similar to the registers presented

in Figure 43, the AFVAROS, BFVAROS, and CFVAROS 24-bit

signed registers are accessed as 32-bit registers with the four

MSBs padded with 0s and sign extended to 28 bits.

HPFEN BIT

DIGITAL

AIGAIN CONFIG3[0] INTEGRATOR

IA

APHCAL

HPF

HPFEN BIT

AVGAIN CONFIG3[0]

VA

HPF

FUNDAMENTAL

REACTIVE

POWER

ALGORITHM

APGAIN AFVAROS

:

DIGITAL SIGNAL PROCESSOR

24

AFVAR

INTERNAL

ACCUMULATOR

THRESHOLD

REVFRPA BIT IN

STATUS0[31:0]

AFVARHR[31:0]

32-BIT REGISTER

34

27 26

0

VARTHR

0

Figure 77. Fundamental Reactive Energy Accumulation

Rev. A | Page 50 of 104

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