ADM1276-3ACPZ-RL(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADM1276-3ACPZ-RL
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADM1276-3ACPZ-RL Datasheet PDF : 48 Pages
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ADM1276
SMBus MESSAGE FORMATS
Figure 52 to Figure 60 show all the SMBus protocols supported
by the ADM1276, along with the PEC variant. In these figures,
unshaded cells indicate that the bus host is actively driving the
bus; shaded cells indicate that the ADM1276 is driving the bus.
Figure 52 to Figure 60 use the following abbreviations:
S is the start condition.
Sr is the repeated start condition.
P is the stop condition.
R is the read bit.
W is the write bit.
A is the acknowledge bit (0).
A is the acknowledge bit (1).
“A” represents the acknowledge bit. The acknowledge bit is typi-
cally active low (Logic 0) if the transmitted byte is successfully
received by a device. However, when the receiving device is the
bus master, the acknowledge bit for the last byte read is a Logic 1,
indicated by A.
S
SLAVE ADDRESS
WA
DATA BYTE
AP
S
SLAVE ADDRESS
WA
DATA BYTE
A
PEC
MASTER TO SLAVE
SLAVE TO MASTER
Figure 52. Send Byte and Send Byte with PEC
AP
S
SLAVE ADDRESS
RA
DATA BYTE
AP
S
SLAVE ADDRESS
RA
DATA BYTE
A
PEC
MASTER TO SLAVE
SLAVE TO MASTER
Figure 53. Receive Byte and Receive Byte with PEC
AP
S
SLAVE ADDRESS
WA
COMMAND CODE
A
DATA BYTE
AP
S
SLAVE ADDRESS
WA
COMMAND CODE
A
DATA BYTE
A
PEC
MASTER TO SLAVE
SLAVE TO MASTER
Figure 54. Write Byte and Write Byte with PEC
AP
S
SLAVE ADDRESS
W A COMMAND CODE
A Sr SLAVE ADDRESS
RA
DATA BYTE
AP
S
SLAVE ADDRESS
WA
COMMAND CODE
A Sr SLAVE ADDRESS
RA
DATA BYTE
A
PEC
MASTER TO SLAVE
SLAVE TO MASTER
Figure 55. Read Byte and Read Byte with PEC
AP
S
SLAVE ADDRESS
W A COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
AP
S
SLAVE ADDRESS
W A COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH A
PEC
MASTER TO SLAVE
SLAVE TO MASTER
Figure 56. Write Word and Write Word with PEC
AP
Rev. 0 | Page 25 of 48
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