ADM1178-2ARMZ-R7(RevPrD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADM1178-2ARMZ-R7
(Rev.:RevPrD)

Hot Swap Controller and Digital Power Monitor with AlertB Output

Analog Devices 

Preliminary Technical Data

WRITE EXTENDED BYTE

In this operation the master device writes to one of the three

extended registers of the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends the register address byte. The MSB

of this byte is set to 1 to indicate an extended register

write. The two LSBs indicate which of the three

extended registers will be written to (see Table 7). All

other bits should be set to 0.

5. The slave asserts ACK on SDA.

6. The master sends the command byte. The command

byte is identified by an MSB = 0. (An MSB = 1

indicates an Extended Register Write. See next

section.)

7. The slave asserts ACK on SDA.

ADM1178

8. The master asserts a STOP condition on SDA to end

the transaction.

1

2

34

5

6

78

S

SLAVE

ADDRESS

R

A

REGISTER

ADDRESS

A

REGISTER

DATA

NP

Figure 11. Command Byte Write

Table 8, Table 9, and give details of each extended register.

Table 7. Extended Register Addresses

A6 A5 A4 A3 A2 A1 A0

0000001

0000010

0000011

Extended Register

ALERT_EN

ALERT_TH

CONTROL

Table 8. ALERT_EN Register Operations

Bit Default Name

Function

00

EN_ADC_OC1 Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH

register

10

EN_ADC_OC4 Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the

ALERT_TH register

21

EN_HS_ALERT Enabled if the hotswap has either latched off, or entered a cool down cycle, because of an overcurrent

event

30

EN_OFF_ALERT Enable an ALERT if the HS operation is turned off by a transition which de-asserts the ON pin, or by an

operation which writes the SWOFF bit high.

40

CLEAR

Clears the ON_ALERT, HS_ALERT and ADC_ALERT status bits in the STATUS register. These may

immediately reset if the source of the alert has not been cleared, or disabled with the other bits in this

register. This bit self-clears to 0 after the STATUS register bits have been cleared.

Table 9. ALERT_TH Register Operations

Bit Default Function

7:0 FF

The ALERT_TH register sets the current level at which an alert will occur. Defaults to ADC full-scale. ALERT_TH 8-bit number

corresponds to the top 8-bits of the current channel data.

Table 10. CONTROL Register Operations

Bit Default

Name

Function

0

0

SWOFF

Force hotswap off. Equivalent to de-asserting the ON pin.

Rev. PrD | Page 13 of 16

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