ADM1178-1ARMZ-R7(RevPrD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADM1178-1ARMZ-R7
(Rev.:RevPrD)

Hot Swap Controller and Digital Power Monitor with AlertB Output

Analog Devices 

ADM1178

Preliminary Technical Data

PIN CONFIGURATIONS

Vcc 1

SENSE 2

ADM1178

10 ALERTB

9 GATE

ON 3

TOP VIEW

8 ADR

GND 4 (NOT TO SCALE) 7 SDA

TIMER 5

6 SCL

Figure 3. Pin Configurations

PIN FUNCTIONAL DESCRIPTIONS

Table 3.

Pin No. Name

Description

1

VCC

Positive supply input pin. The operating supply voltage range is between 3.15 V to 14 V. An undervoltage

lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected.

2

SENSE

Current sense input pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. The

hotswap operation of the ADM1178 controls the external FET gate to maintain the (VVCC-VSENSE) voltage at 100

mV or below.

3

ON

Undervoltage input pin. Aactive high pin. An internal ON comparator has a trip threshold of 1.3 V and the

output of this comparator is used as an enable for the hotswap operation. With an external resistor divider

from VCC to GND, this pin can be used to enable the hotswap operation one a specific voltage on VCC, giving

an undervoltage function.

4

GND

Chip Ground Pin

5

TIMER

Timer pin. An external capacitor CTIMER sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay.

The GATE pin turns off whenever the TIMER pin is pulled beyond the upper threshold. An overvoltage

detection with an external zener can be used to force this pin high.

6

SCL

I2C Clock Pin. Open-drain output requires an external resistive pull-up.

7

SDA

I2C Data I/O Pin. Open-drain output requires an external resistive pull-up.

8

ADR

I2C Address Pin. This pin can be tied low, tied high, left floating or tied low through a resistor to set four

different I2C addresses.

9

GATE

GATE Output Pin. This pin is the high side gate drive of an external N-channel FET. This pin is driven by the FET

drive controller which utilises a charge pump to provide a 12 µA pull-up current to charge the FET gate pin.

The FET drive controller regulates to a maximum load current (100 mV through the sense resistor) by

modulating the GATE pin.

10

ALERTB

Alert Output Pin. Active low, open drain configuration. This pin asserts when an overcurrent condition is

present.

Rev. PrD | Page 6 of 16

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