ADP3050ARZ-3.3-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3050ARZ-3.3-RL Datasheet PDF : 20 Pages
| |||
Data Sheet
BOARD LAYOUT GUIDELINES
A good board layout is essential when designing a switching
regulator. The high switching currents along with parasitic
wiring inductances can generate significant voltage transients
and cause havoc in sensitive circuits. For best results, keep the
main switching path as tight as possible (keep L1, D1, CIN, and
COUT close together) and minimize the copper area of the SWITCH
and BOOST nodes (without violating current density require-
ments) to reduce the amount of noise coupling into other
sensitive nodes.
VIN
IN
SWITCH
L1
VOUT
CIN
GND
ADP3050
GND
D1
COUT
GND
Figure 26. Main Switching Path
The external components should be located as close to the
ADP3050 as possible. For best thermal performance, use wide
copper traces for all IC connections, and always connect the
GND pin to a large piece of copper or ground plane. The additional
copper improves heat transfer from the IC, greatly reducing the
package thermal resistance. Further improvements of the thermal
performance can be made by using multilayer boards and using
vias to transfer heat to the other layers. A single layer board
layout is shown in Figure 27. The amount of copper used for the
input, output, and ground traces can be reduced, but were made
large to improve the thermal performance. For the 5 V and 3.3 V
versions, leave out R1 and R2; for the adjustable version, remove
the trace that shorts out R2. Route all sensitive traces and compo-
nents, such as those associated with feedback and compensation,
away from the BOOST and SWITCH traces.
TYPICAL APPLICATIONS
5 V to 3.3 V Buck (Step-Down) Regulator
The circuit in Figure 28 shows the ADP3050 in a buck
configuration. It is used to generate 3.3 V regulated output from
5 V input voltage with the following specifications:
VIN = 4.5 V to 5.5 V
VOUT = 3.3 V
IOUT = 0.75 A
IRIPPLE = 0.4 A × 0.75 A = 0.3 A
VOUT_RIPPLE = 50 mV
ADP3050
OUTPUT
GROUND
C1
INPUT
C3
L1
D1
D2
C2
R2
R1
CC
RC
ADP3050
Figure 27. Recommended Board Layout
D1
1N5817
L1
22µH
D2
1N4148
C3
0.22µF
SD
5V
VIN
GND
+ C1
22µF
1 SWITCH IN 8
3.3V
VOUT
+ C5
100µF
2 BOOST GND 7
3 BIAS
SD 6
4 FB COMP 5
R1
U1
7.5kΩ
ADP3050-3.3
C4
1nF
C2
0.01µF
Figure 28. 5 V to 3.3 V Buck Regulator
Rev. C | Page 17 of 20
Share Link: 