ADP3198JCPZ-RL View Datasheet(PDF) - Analog Devices
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ADP3198JCPZ-RL Datasheet PDF : 32 Pages
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ADP3198
THEORY OF OPERATION
The ADP3198 combines a multimode, fixed frequency,
PWM control with multiphase logic outputs for use in 2-, 3-,
and 4-phase synchronous buck CPU core supply power
converters. The internal VID DAC is designed to interface
with the Intel 8-bit VRD/VRM 11-compatible and 7-bit
VRD/VRM 10×-compatible CPUs. Multiphase operation is
important for producing the high currents and low voltages
demanded by today’s microprocessors. Handling the high
currents in a single-phase converter places high thermal
demands on the components in the system, such as the
inductors and MOSFETs.
The multimode control of the ADP3198 ensures a stable,
high performance topology for the following:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses by using lower
frequency operation
• Tight load line regulation and accuracy
• High current output due to 4-phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE
The ADP3198 follows the VR11 start-up sequence shown in
Figure 7. After both the EN and UVLO conditions are met,
the DELAY pin goes through one cycle (TD1). The first four
clock cycles of TD2 are blanked from the PWM outputs and
used for phase detection as explained in the Phase Detection
Sequence section. Then, the soft start ramp is enabled (TD2),
and the output comes up to the boot voltage of 1.1 V. The boot
hold time is determined by the DELAY pin as it goes through a
second cycle (TD3). During TD3, the processor VID pins settle
to the required VID code. When TD3 is over, the ADP3198 soft
starts either up or down to the final VID voltage (TD4). After
TD4 is completed and the PWRGD masking time (equal to VID
on-the-fly masking) is completed, a third ramp on the DELAY
pin sets the PWRGD blanking (TD5).
5V
SUPPLY
UVLO
THRESHOLD
VTT I/O
(ADP3198 EN)
DELAY
0.85V
VDELAY(TH)
(1.7V)
SS
VCC_CORE
VR READY
(ADP3198 PWRGD)
CPU
VID INPUTS
TD1
VBOOT
1V
(1.1V)
TD3
VBOOT
(1.1V)
TD2
VVID
VVID
TD4
TD5
50µs
VID INVALID
VID VALID
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3198 operates
as a 4-phase PWM controller. Connecting the PWM4 pin to
VCC programs 3-phase operation and connecting the PWM4
and PWM3 pins to VCC programs 2-phase operation.
Prior to soft start, while EN is low, the PWM3 and PWM4 pins
sink approximately 100 μA. An internal comparator checks each
pin’s voltage vs. a threshold of 3 V. If the pin is tied to VCC, it is
above the threshold. Otherwise, an internal current sink pulls
the pin to GND, which is below the threshold. PWM1 and
PWM2 are low during the phase detection interval that occurs
during the first four clock cycles of TD2. After this time, if the
remaining PWM outputs are not pulled to VCC, the 100 μA
current sink is removed, and they function as normal PWM
outputs. If they are pulled to VCC, the 100 μA current source is
removed, and the outputs are put into a high impedance state.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3110A. Because each
phase is monitored independently, operation approaching 100%
duty cycle is possible. In addition, more than one output can be
on at the same time to allow overlapping phases.
Rev. A | Page 10 of 32
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