ADP7105ARDZ-5.0(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP7105ARDZ-5.0 Datasheet PDF : 28 Pages
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ADP7105
Data Sheet
POWER-GOOD FEATURE
The ADP7105 provides a power-good pin (PG) to indicate
the status of the output. This open-drain output requires an
external pull-up resistor to VIN or VOUT. If the part is in
shutdown mode, current-limit mode, or thermal shutdown, or
if VOUT falls below 90% of the nominal output voltage, the
power-good pin (PG) immediately transitions low. During soft
start, the rising threshold of the power-good signal is 93.5% of
the nominal output voltage.
The open-drain output is held low when the ADP7105 has suffi-
cient input voltage to turn on the internal PG transistor. The PG
transistor is terminated via a pull-up resistor to VOUT or VIN.
Power-good accuracy is 93.5% of the nominal regulator output
voltage when this voltage is rising, with a 90.8% trip point when
this voltage is falling. Regulator input voltage brownouts or
glitches trigger power no good signals if VOUT falls below 90.8%
of the nominal output voltage.
A normal power-down causes the power-good signal to go low
when VOUT falls below 90.8%.
Figure 68 and Figure 69 show the typical power-good rising and
falling thresholds over temperature.
6
–40°C
–5°C
+25°C
5 +85°C
+125°C
4
3
2
1
NOISE REDUCTION OF THE ADJUSTABLE
ADP7105
The ultralow output noise of the fixed output ADP7105 is
achieved by keeping the LDO error amplifier in unity gain
and setting the reference voltage equal to the output voltage.
This architecture does not apply to the adjustable output voltage
LDO regulator. The adjustable output ADP7105 uses the more
conventional architecture where the reference voltage is fixed
and the error amplifier gain is a function of the output voltage.
The disadvantage of the conventional LDO architecture is that
the output voltage noise is proportional to the output voltage.
The adjustable LDO circuit can be modified slightly to reduce
the output voltage noise to levels close to that of the fixed output
ADP7105. The circuit shown in Figure 70 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be equal to RFB2. This limits
the ac gain of the error amplifier to approximately 6 dB. The
actual gain is the parallel combination of RNR and RFB1 divided
by RFB2. This ensures that the error amplifier always operates at
greater than unity gain.
CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR
at a frequency between 50 Hz and 100 Hz. This capacitor value sets
the frequency so that the ac gain of the error amplifier is 3 dB
less than its dc gain.
VIN = 8V
CIN +
1µF
ON
R3
100kΩ
OFF
R4
100kΩ
VIN VOUT
RFB1
40.2kΩ
ADJ
+ CNR
100nF
+
VOUT
COUT
=
5V
1µF
EN/
UVLO
RFB2
13kΩ
RNR
13kΩ
RPG
100kΩ
PG
PG
GND SS
CSS
0
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
VOUT (V)
Figure 68. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Rising
6
–40°C
–5°C
+25°C
5 +85°C
+125°C
Figure 70. Noise Reduction Modification to Adjustable LDO Regulator
The noise of the adjustable LDO regulator can be found by
using the following formula, assuming the noise of a fixed
output LDO is approximately 15 μV:
15μV ×
1
+
1/13
kΩ
1
+1/
40.2
kΩ
/ 13
kΩ
4
Based on the component values shown in Figure 70, the
ADP7105 has the following characteristics:
3
• DC gain of 4.09 (12.2 dB)
2
• 3 dB roll-off frequency of 59 Hz
• High frequency ac gain of 1.76 (4.89 dB)
1
• Noise reduction factor of 1.33 (2.59 dB)
• RMS noise of the ADP7105 adjustable LDO without noise
0
4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0
VOUT (V)
Figure 69. Typical Power-Good Threshold vs. Output Voltage and
Temperature, VOUT Falling
reduction of 27.8 µV rms
• RMS noise of the ADP7105 adjustable LDO with noise
reduction (assuming 15 µV rms for fixed voltage option)
of 19.95 µV rms
Rev. 0 | Page 20 of 28
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