ADSP-21363(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-21363 Datasheet PDF : 52 Pages
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Master
The ADSP-2136x contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in Table 38 and Table 39 applies to both.
Table 38. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Min
Timing Requirements
tSSPIDM
tSSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2
Data Input Valid to SPICLK Edge (Data Input Setup Time) 8.2
(SPI2)
tHSPIDM
SPICLK Last Sampling Edge to Data
2
Input Not Valid
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid
(Data Out Delay Time)
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
tDDSPIDM
SPICLK Edge to Data Out Valid
(Data Out Delay Time) (SPI2)
tHDSPIDM
SPICLK Edge to Data Out Not Valid
2
(Data Out Hold Time)
tSDSCIM
tSDSCIM
tHDSM
tSPITDM
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × tPCLK – 2.5
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × tPCLK – 2.5
Last SPICLK Edge to FLAG3–0IN High
4 × tPCLK – 2
Sequential Transfer Delay
4 × tPCLK – 1
Max
3.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 41 of 52 | December 2006
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