AD8111AST(2002) View Datasheet(PDF) - Analog Devices
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AD8111AST Datasheet PDF : 28 Pages
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The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to
“wire-OR” the outputs together in the vertical direction. The
meaning of horizontal and vertical can best be understood by
looking at a diagram. Figure 6 illustrates this concept for a 32 × 8
crosspoint array.
IN 00–15
16
16
RTERM
AD8110
OR
AD8111
8
IN 16–31
16
16
RTERM
AD8110
OR
AD8111
8
Figure 6. A 32 × 8 Crosspoint Array Using Two AD8110s
or Two AD8111s
The inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. The outputs
are wire-ORed together in pairs. The output from only one of a
wired OR pair should be enabled at any given time. The device
programming software must be properly written to cause this
to happen.
AD8110/AD8111
At some point, the number of outputs that are wire-ORed becomes
too great to maintain system performance. This will vary according
to which system specifications are most important. It will also depend
on whether the matrix consists of AD8110s or AD8111s. The
output disabled impedance of the AD8110 is much higher than
that of the AD8111, so its disabled parasitics will have a smaller
effect on the one output that is enabled. For example, a 128 × 8
crosspoint can be created with eight AD8110/AD8111s. This
design will have 128 separate inputs and have the corresponding
outputs of each device wire-ORed together in groups of eight.
Using additional crosspoint devices in the design can lower the
number of outputs that must be wire-ORed together. Figure 7
shows a block diagram of a system using eight AD8110s and
two AD8111s to create a nonblocking, gain-of-two, 128 × 8
crosspoint that restricts the wire-ORing at the output to only
four outputs. These devices are the AD8110, which has a higher
disabled output impedance than the AD8111.
Additionally, by using the lower four outputs from each of the
two Rank 2 AD8111s, a blocking 128 × 16 crosspoint array can
be realized. There are, however, some drawbacks to this tech-
nique. The offset voltages of the various cascaded devices will
accumulate and the bandwidth limitations of the devices will
compound. In addition, the extra devices will consume more
current and take up more board space. Once again, the overall
system design specifications will determine how to make the
various tradeoffs.
REV. A
IN 00–15
16
RTERM
IN 16–31
16
RTERM
IN 32–47
16
RTERM
IN 48–63
16
RTERM
IN 64–79
16
RTERM
IN 80–95
16
RTERM
IN 96–111
16
RTERM
IN 112–127
16
RTERM
RANK 1
(8 x AD8110)
128:16
4
AD8110 4
4
AD8110 4
4
AD8110 4
4
AD8110 4
4
AD8110 4
4
AD8110 4
4
AD8110 4
4
AD8110 4
RANK 2
16:8 NONBLOCKING
(16:16 BLOCKING)
4
1k⍀
AD8111
4
1k⍀
4
1k⍀
AD8111
4
1k⍀
4
OUT 00 – 07
4
NONBLOCKING
4
ADDITIONAL
8 OUTPUTS
4
(SUBJECT
TO BLOCKING)
Figure 7. A Gain-of-Two 128 × 8 Nonblocking Crosspoint Array (128 × 16 Blocking)
–17–
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