Table 42. KBLS Register
KBLS - Keyboard Level Selector Register (9Ch)
7
6
5
4
3
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
2
KBLS2
1
KBLS1
Bit
Number
7
6
5
4
3
2
1
0
Bit
Mnemonic Description
KBLS7
Keyboard line 7 level selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
KBLS6
Keyboard line 6 level selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
KBLS5
Keyboard line 5 level selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
KBLS4
Keyboard line 4 level selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
KBLS3
Keyboard line 3 level selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
KBLS2
Keyboard line 2 level selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
KBLS1
Keyboard line 1 level selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
KBLS0
Keyboard line 0 level selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
0
KBLS0
58 AT80C51RD2/AT83C51Rx2
4113B–8051–03/05