AT89C51RC2-3CSCM(2003) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT89C51RC2-3CSCM Datasheet PDF : 125 Pages
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Enhanced Features
X2 Feature
Description
In comparison to the original 80C52, the AT89C51RB2/RC2 implements some new fea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI interface
• 4-level interrupt priority system
• power-off flag
• ONCE mode
• ALE disabling
• Some enhanced features are also located in the UART and the timer 2
The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
The clock for the whole circuit and peripherals is first divided by 2 before being used by
the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 4 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid glitches when switching from X2 to X1 mode. Figure 5 shows
the switching mode waveforms.
Figure 4. Clock Generation Diagram
CKRL
XTAL1
FXTAL
XTAL1:2
FOSC
2
0
8 bit Prescaler
1
FCLK CPU
FCLK PERIPH
X2
CKCON0
14 AT89C51RB2/RC2
4180B–8051–04/03
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