AT89C51RB2/RC2
Table 48. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
6
5
4
-
-
-
-
3
2
1
-
SPIL
-
Bit
Number
7
Bit
Mnemonic Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
SPIL
SPI Interrupt Priority Bit
see SPIH for priority level.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
KBDL
Keyboard Interrupt Priority Bit
see KBDH for priority level.
Reset Value = XXXX X000b
Bit addressable
0
KBDL
59
4180B–8051–04/03