Figure 22. Single Cycle ALU Operation
T1
T2
T3
T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 23.
Figure 23. On-chip Data SRAM Access Cycles
T1
T2
T3
T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
I/O Memory
The I/O space definition of the ATmega323 is shown in Table 2.
Table 2. ATmega323 I/O Space
I/O Address (SRAM
Address)
Name
$3F ($5F)
SREG
$3E ($5E)
SPH
$3D ($5D)
SPL
$3C ($3C)
OCR0
$3B ($5B)
GICR
$3A ($5A)
GIFR
$39 ($59)
TIMSK
$38 ($58)
TIFR
$37 ($57)
SPMCR
$36 ($56)
TWCR
$35 ($55)
MCUCR
$34 ($54)
MCUCSR
Function
Status Register
Stack Pointer High
Stack Pointer Low
Timer/Counter0 Output Compare Register
General Interrupt Control Register
General Interrupt Flag Register
Timer/Counter Interrupt Mask Register
Timer/Counter Interrupt Flag Register
SPM Control Register
Two-wire Serial Interface Control Register
MCU general Control Register
MCU general Control and Status Register
18 ATmega323(L)
1457G–AVR–09/03