ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

Reading the Fuse and Lock

Bits from Software

Preventing Flash Corruption

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,

load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR.

When an LPM instruction is executed within three CPU cycles after the BLBSET and

SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destina-

tion register. The BLBSET and SPMEN bits will auto-clear upon completion of reading

the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM

instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared,

LPM will work as described in the AVR Instruction Set Reference Manual.

Bit

7

6

5

4

3

2

1

0

Rd

–

–

BLB12 BLB11 BLB02 BLB01

LB2

LB1

The algorithm for reading the Fuse Low bits is similar to the one described above for

reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with 0x0000 and set

the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within

three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the

Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to

Table 120 on page 292 for a detailed description and mapping of the Fuse Low bits.

Bit

7

6

5

4

3

2

1

0

Rd

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Similarly, when reading the Fuse High bits, load 0x0003 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCSR, the value of the Fuse High bits (FHB) will be loaded in the destination

register as shown below. Refer to Table 119 on page 292 for detailed description and

mapping of the Fuse High bits.

Bit

7

6

5

4

3

2

1

0

Rd

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

When reading the Extended Fuse bits, load 0x0002 in the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCSR, the value of the Extended Fuse bits (EFB) will be loaded in the destina-

tion register as shown below. Refer to Table 118 on page 291 for detailed description

and mapping of the Fuse High bits.

Bit

7

6

5

4

3

2

1

0

Rd

–

–

–

–

–

–

EFB1

EFB0

Fuse and Lock bits that are programmed will be read as zero. Fuse and Lock bits that

are unprogrammed will be read as one.

During periods of low VCC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU and the Flash to operate properly. These issues are the same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program corruption can be caused by two situations when the voltage is too low.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rectly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage

for executing instructions is too low.

Flash corruption can easily be avoided by following these design recommendations (one

is sufficient):

286 ATmega64(L)

2490G–AVR–03/04

Share Link: