Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
4 MHz Oscillator
Variable Oscillator
Symbol Parameter
Min
Max
Min
Max
13 tDVWL
Data Setup to WR Low
105
0.5tCLCL-20(1)
14 tWHDX
Data Hold After WR High
235
1.0tCLCL-15
15 tDVWH
Data Valid to WR High
250
1.0tCLCL
16 tWLWH
WR Pulse Width
235
1.0tCLCL-15
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
4 MHz Oscillator
Variable Oscillator
Symbol Parameter
Min
Max
Min
Max
0 1/tCLCL
10 tRLDV
12 tRLRH
15 tDVWH
16 tWLWH
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Valid to WR High
WR Pulse Width
0.0
8
440
2.0tCLCL-60
485
2.0tCLCL-15
500
2.0tCLCL
485
2.0tCLCL-15
Unit
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator
Variable Oscillator
Symbol Parameter
Min
Max
Min
Max
0 1/tCLCL
10 tRLDV
12 tRLRH
15 tDVWH
16 tWLWH
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Valid to WR High
WR Pulse Width
0.0
8
690
3.0tCLCL-60
735
3.0tCLCL-15
750
3.0tCLCL
735
3.0tCLCL-15
Table 145. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator
Variable Oscillator
Symbol Parameter
Min
Max
Min
Max
0 1/tCLCL
Oscillator Frequency
0.0
8
10 tRLDV
Read Low to Data Valid
690
3.0tCLCL-60
12 tRLRH
RD Pulse Width
735
3.0tCLCL-15
14 tWHDX
Data Hold After WR High
485
2.0tCLCL-15
15 tDVWH
Data Valid to WR High
750
3.0tCLCL
16 tWLWH
WR Pulse Width
735
3.0tCLCL-15
Unit
MHz
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
338 ATmega64(L)
2490G–AVR–03/04