ATMEGA64L-8MI View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

ATMEGA64L-8MI

8-bit AVR® Microcontroller with 64K Bytes In-System Programmable Flash

Atmel Corporation 

Errata

ATmega64, all rev.

2490G–AVR–03/04

ATmega64(L)

The revision letter in this section refers to the revision of the ATmega64 device.

• Stabilizing time needed when changing XDIV Register

• Stabilizing time needed when changing OSCCAL Register

1. Stabilizing time needed when changing XDIV Register

After increasing the source clock frequency more than 2% with settings in the XDIV

register, the device may execute some of the subsequent instructions incorrectly.

Problem Fix / Workaround

The NOP instruction will always be executed correctly also right after a frequency

change. Thus, the next 8 instructions after the change should be NOP instructions.

To ensure this, follow this procedure:

1.Clear the I bit in the SREG Register.

2.Set the new pre-scaling factor in XDIV register.

3.Execute 8 NOP instructions

4.Set the I bit in SREG

This will ensure that all subsequent instructions will execute correctly.

Assembly Code Example:

CLI

; clear global interrupt enable

OUT XDIV, temp ; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; clear global interrupt enable

2. Stabilizing time needed when changing OSCCAL Register

After increasing the source clock frequency more than 2% with settings in the OSC-

CAL register, the device may execute some of the subsequent instructions

incorrectly.

Problem Fix / Workaround

The behavior follows errata number 1., and the same Fix / Workaround is applicable

on this errata.

A proposal for solving problems regarding the JTAG instruction IDCODE is presented

below.

IDCODE masks data from TDI input

The public but optional JTAG instruction IDCODE is not implemented correctly

according to IEEE1149.1; a logic one is scanned into the shift register instead of the

TDI input while shifting the Device ID Register. Hence, captured data from the pre-

ceding devices in the boundary scan chain are lost and replaced by all-ones, and

data to succeeding devices are replaced by all-ones during Update-DR.

If ATmega64 is the only device in the scan chain, the problem is not visible.

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