XMEGA D4
32.6 ADC characteristics
Table 32-8. Power supply, reference and input range.
Symbol Parameter
Condition
AVCC
VREF
Rin
Csample
RAREF
CAREF
VIN
Analog supply voltage
Reference voltage
Input resistance
Input capacitance
Reference input resistance
Reference input capacitance
Input range
Conversion range
Switched
Switched
(leakage only)
Static load
Differential mode, Vinp - Vinn
VIN
Conversion range
ΔV
Fixed offset voltage
Single ended unsigned mode, Vinp
Min.
VCC- 0.3
1
-0.1
-VREF
-ΔV
Typ.
4.0
4.4
>10
7
190
Max.
VCC+ 0.3
AVCC- 0.6
AVCC+0.1
VREF
VREF-ΔV
Units
V
kΩ
pF
MΩ
pF
V
LSB
Table 32-9. Clock and timing.
Symbol Parameter
ClkADC ADC Clock frequency
fADC
Sample rate
Sampling Time
Conversion time (latency)
Start-up time
ADC settling time
Condition
Maximum is 1/4 of Peripheral clock
frequency
Measuring internal signals
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
1/2 ClkADC cycle
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0, 1, 2, or 3
ADC clock cycles
After changing reference or input mode
After ADC flush
Min.
100
100
14
14
14
14
0.25
5
Typ.
7
12
7
1
Max.
1400
125
200
150
100
50
5
10
24
7
1
Units
kHz
ksps
µs
ClkADC
cycles
ClkADC
cycles
Table 32-10. Accuracy characteristics.
Symbol Parameter
Condition (2)
RES
Resolution
Programmable to 8 or 12 bit
INL (1) Integral non-linearity
DNL (1) Differential non-linearity
50ksps
VCC-1.0V < VREF < VCC-0.6V
All VREF
200ksps
VCC-1.0V < VREF < VCC-0.6V
All VREF
guaranteed monotonic
Min.
8
Typ.
12
±1.2
±1.5
±1.0
±1.5
<±0.8
Max.
12
±3
±4
±3
±4
<±1
Units
Bits
lsb
70
8135L–AVR–06/12