Table 32-29. Two-wire interface characteristics. (Continued)
Symbol Parameter
Condition
tHD;STA Hold time (repeated) START condition
tLOW
Low period of SCL clock
tHIGH
tSU;STA
High period of SCL Clock
Set-up time for a repeated START
condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO Setup time for STOP condition
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
Notes:
1. Required only for fSCL > 100kHz.
2. Cb = Capacitance of one bus line in pF.
3. fPER = Peripheral clock frequency.
XMEGA D4
Min.
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
0
0
250
100
4.0
0.6
4.7
1.3
Typ.
Max. Units
µs
3.45
0.9
µs
84
8135L–AVR–06/12