ATXMEGA64A1-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
ATXMEGA64A1-CU Datasheet PDF : 107 Pages
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XMEGA A1
7.7 Flash and EEPROM Page Size
Devices
ATxmega64A1
ATxmega128A1
ATxmega192A1
ATxmega256A1
ATxmega384A1
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 15 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Flash
Page Size
FWORD
FPAGE
Application
Size (Bytes)
(words)
Size (Bytes) No of Pages
64K + 4K
128
Z[7:1]
Z[16:8]
64K
256
128K + 8K
256
Z[8:1]
Z[17:9]
128K
256
192K + 8K
256
Z[8:1]
Z[18:9]
192K
384
256K + 8K
256
Z[8:1]
Z[18:9]
256K
512
384K + 8K
256
Z[8:1]
Z[19:9]
384K
768
Boot
Size (Bytes) No of Pages
4K
16
8K
16
8K
16
8K
16
8K
16
Devices
ATxmega64A1
ATxmega128A1
ATxmega192A1
ATxmega256A1
ATxmega384A1
Table 7-3 on page 15 shows EEPROM memory organization for the XMEGA A1 devices.
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
EEPROM
Size
2 KB
2 KB
2 KB
4 KB
4 KB
Number of Bytes and Pages in the EEPROM.
Page Size
E2BYTE
E2PAGE
(Bytes)
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[11:5]
32
ADDR[4:0]
ADDR[11:5]
No of Pages
64
64
64
128
128
15
8067L–AVR–08/10
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