C8051F012 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F012 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only)
The ADC subsystem for the C8051F010/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 10-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 6.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 6.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 6.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.
Figure 6.1. 10-Bit ADC Functional Block Diagram
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
+
-
+
- 9-to-1
+ AMUX
(SE or
- DIFF)
+
-
TEMP
SENSOR
AGND
ADCEN
AV+
X
+
-
AGND
AV+
10-Bit
SAR
10
ADC
20
10
COMB
LOGIC
ADWINT
TMR3 OV
T2 OV
CNVSTR
ADBUSY(w)
AMX0CF
AMX0SL
ADC0CF
ADC0CN
6.1. Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 6.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 6.5),
and the Configuration register AMX0CF (Figure 6.4). The table in Figure 6.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 6.6). The PGA can be software-
programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
Rev. 1.7
40
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