C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 7.2. DAC0H: DAC0 High Byte Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bits7-0: DAC0 Data Word Most Significant Byte.
R/W
Reset Value
00000000
Bit0
SFR Address:
0xD3
Figure 7.3. DAC0L: DAC0 Low Byte Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bits7-0: DAC0 Data Word Least Significant Byte.
R/W
Reset Value
00000000
Bit0
SFR Address:
0xD2
Figure 7.4. DAC0CN: DAC0 Control Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
DAC0EN
-
-
-
-
DAC0DF2 DAC0DF1 DAC0DF0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xD4
Bit7: DAC0EN: DAC0 Enable Bit
0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low power shutdown mode.
1: DAC0 Enabled. DAC0 Output is pin active; DAC0 is operational.
Bits6-3: UNUSED. Read = 0000b; Write = don’t care
Bits2-0: DAC0DF2-0: DAC0 Data Format Bits
000: The most significant nybble of the DAC0 Data Word is in DAC0H[3:0], while the least significant
byte is in DAC0L.
DAC0H
DAC0L
MSB
LSB
001: The most significant 5-bits of the DAC0 Data Word is in DAC0H[4:0], while the least significant
7-bits is in DAC0L[7:1].
DAC0H
DAC0L
MSB
LSB
010: The most significant 6-bits of the DAC0 Data Word is in DAC0H[5:0], while the least significant
6-bits is in DAC0L[7:2].
DAC0H
DAC0L
MSB
LSB
011: The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least significant
5-bits is in DAC0L[7:3].
DAC0H
DAC0L
MSB
LSB
1xx: The most significant byte of the DAC0 Data Word is in DAC0H, while the least significant nybble
is in DAC0L[7:4].
DAC0H
DAC0L
MSB
LSB
Rev. 1.7
52