C8051F012 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F012

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

10. CIP-51 CPU

The MCUs’ system CPU is the CIP-51. The CIP-51 is fully compatible with the MCS-51TM instruction set.

Standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of

all the peripherals included with a standard 8051. Included are four 16-bit counter/timers (see description in Section

19), a full-duplex UART (see description in Section 18), 256 bytes of internal RAM, 128 byte Special Function

Register (SFR) address space (see Section 10.3), and four byte-wide I/O Ports (see description in Section 14). The

CIP-51 also includes on-chip debug hardware (see description in Section 21), and interfaces directly with the

MCUs’ analog and digital subsystems providing a complete data acquisition or control-system solution in a single

integrated circuit.

Features

The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional

custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram). The CIP-51

includes the following features:

- Fully Compatible with MCS-51 Instruction Set

- 25 MIPS Peak Throughput with 25MHz Clock

- 0 to 25MHz Clock Frequency (on ‘F0x5/6/7)

- Four Byte-Wide I/O Ports

- Extended Interrupt Handler

- Reset Input

- Power Management Modes

- On-chip Debug Circuitry

- Program and Data Memory Security

Figure 10.1. CIP-51 Block Diagram

DATA BUS

ACCUMULATOR

TMP1

TMP2

PSW

ALU

B REGISTER

STACK POINTER

SRAM

ADDRESS

REGISTER

SRAM

(256 X 8)

DATA BUS

BUFFER

D8

DATA POINTER

D8

PC INCREMENTER

SFR_ADDRESS

SFR_CONTROL

SFR

D8

BUS

SFR_WRITE_DATA

INTERFACE

SFR_READ_DATA

PROGRAM COUNTER (PC)

PRGM. ADDRESS REG.

RESET

CLOCK

CONTROL

LOGIC

PIPELINE

STOP

IDLE

POWER CONTROL

REGISTER

D8

D8

MEM_ADDRESS

MEM_CONTROL

MEMORY

A16

INTERFACE MEM_WRITE_DATA

MEM_READ_DATA

D8

INTERRUPT

D8

INTERFACE

SYSTEM_IRQs

EMULATION_IRQ

Rev. 1.7

62

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