C8051F012 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F012 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.3.1. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should
not be set to logic l. Future product versions may use these bits to implement new features in which case the reset
value of the bit will be logic 0, selecting the feature’s default state. Detailed descriptions of the remaining SFRs are
included in the sections of the datasheet associated with their corresponding system function.
Figure 10.3. SP: Stack Pointer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7-0: SP: Stack Pointer.
The stack pointer holds the location of the top of the stack. The stack pointer is
incremented before every PUSH operation. The SP register defaults to 0x07 after reset.
Reset Value
00000111
SFR Address:
0x81
Figure 10.4. DPL: Data Pointer Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x82
Bits 7-0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
Figure 10.5. DPH: Data Pointer High Byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7-0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed RAM and Flash Memory.
Reset Value
00000000
SFR Address:
0x83
Rev. 1.7
74
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