C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 16.3. EMI0TC: External Memory Timing Control

R/W

EAS1

Bit7

R/W

EAS0

Bit6

R/W

ERW3

Bit5

R/W

EWR2

Bit4

R/W

EWR1

Bit3

R/W

EWR0

Bit2

Bits7-6:

Bits5-2:

Bits1-0:

EAS1-0: EMIF Address Setup Time Bits.

00: Address setup time = 0 SYSCLK cycles.

01: Address setup time = 1 SYSCLK cycle.

10: Address setup time = 2 SYSCLK cycles.

11: Address setup time = 3 SYSCLK cycles.

EWR3-0: EMIF /WR and /RD Pulse-Width Control Bits.

0000: /WR and /RD pulse width = 1 SYSCLK cycle.

0001: /WR and /RD pulse width = 2 SYSCLK cycles.

0010: /WR and /RD pulse width = 3 SYSCLK cycles.

0011: /WR and /RD pulse width = 4 SYSCLK cycles.

0100: /WR and /RD pulse width = 5 SYSCLK cycles.

0101: /WR and /RD pulse width = 6 SYSCLK cycles.

0110: /WR and /RD pulse width = 7 SYSCLK cycles.

0111: /WR and /RD pulse width = 8 SYSCLK cycles.

1000: /WR and /RD pulse width = 9 SYSCLK cycles.

1001: /WR and /RD pulse width = 10 SYSCLK cycles.

1010: /WR and /RD pulse width = 11 SYSCLK cycles.

1011: /WR and /RD pulse width = 12 SYSCLK cycles.

1100: /WR and /RD pulse width = 13 SYSCLK cycles.

1101: /WR and /RD pulse width = 14 SYSCLK cycles.

1110: /WR and /RD pulse width = 15 SYSCLK cycles.

1111: /WR and /RD pulse width = 16 SYSCLK cycles.

EAH1-0: EMIF Address Hold Time Bits.

00: Address hold time = 0 SYSCLK cycles.

01: Address hold time = 1 SYSCLK cycle.

10: Address hold time = 2 SYSCLK cycles.

11: Address hold time = 3 SYSCLK cycles.

R/W

EAH1

Bit1

R/W

Reset Value

EAH0 11111111

Bit0

SFR Address: 0xA1

SFR Page: 0

Rev. 1.5

195

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