C8051F045 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F045 Datasheet PDF : 328 Pages
| |||
C8051F040/1/2/3/4/5/6/7
Figure 19.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between
3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional
SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free.
The maximum number of devices on the bus is limited only by the requirement that the rise and fall times
on the bus will not exceed 300 ns and 1000 ns, respectively.
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
Master
Device
Slave
Device 1
Slave
Device 2
SDA
SCL
Figure 19.2. Typical SMBus Configuration
19.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
• I2C Manual (AN10216-01) -- March 24, 2003, Philips Semiconductor.
• System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
240
Rev. 1.5
Share Link: 