C8051F045 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

SFR Definition 5.5. ADC0CF: ADC0 Configuration Register

R/W

AD0SC4

Bit7

R/W

AD0SC3

Bit6

R/W

AD0SC2

Bit5

R/W

AD0SC1

Bit4

R/W

R/W

R/W

R/W

Reset Value

AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 11111000

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xBC

SFR Page: 0

Bits7-3:

AD0SC4-0: ADC0 SAR Conversion Clock Period Bits

SAR Conversion clock is derived from system clock by the following equation, where

AD0SC refers to the 5-bit value held in AD0SC4-0, and CLKSAR0 refers to the desired ADC0

SAR clock. See Table 5.2 for SAR clock configuration requirements.

AD0SC  -S---Y----S---C-----L---K--- – 1 *

CLKSAR0

or

CLKSAR0

=

----S---Y----S---C----L----K------

AD0SC + 1

*Note: AD0SC is the rounded-up result.

Bits2-0:

AMP0GN2-0: ADC0 Internal Amplifier Gain (PGA)

000: Gain = 1

001: Gain = 2

010: Gain = 4

011: Gain = 8

10x: Gain = 16

11x: Gain = 0.5

58

Rev. 1.5

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