C8051F066 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F066

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F060/1/2/3/4/5/6/7

6. Direct Memory Access Interface (DMA0)

The DMA interface works in conjunction with ADC0 and ADC1 to write ADC outputs directly to a specified

region of XRAM. The DMA interface is configured by software using the Special Function Registers shown

in Figure 6.1. Up to 64 instructions can be programmed into the Instruction Buffer to designate a sequence

of DMA operations. The Instruction Buffer is accessed by the DMA Control Logic, which gathers the appro-

priate data from the ADCs and controls writes to XRAM. The DMA instructions tell the DMA Control Logic

which ADC(s) to expect results from, but do not initiate the actual conversions. It is important to configure

the ADCs for the desired start-of-conversion source, voltage reference, and SAR clock frequency prior to

starting the DMA interface. For information on setting up the ADCs, refer to Section “5. 16-Bit ADCs (ADC0

and ADC1)” on page 51.

Address

DMA0IPT

Figure 6.1. DMA0 Block Diagram

Instruction Data

DMA0IDT

DMA0CF

DMA0CN

Current Address

DMA0ISW

Start Address

DMA0BND

Write Logic

Instruction

Buffer

(64 Bytes)

DMA

Control Logic

Address Bus

Data Bus

XRAM

(on-chip or

off-chip)

AIN0

AIN0G

AIN1

AIN1G

ADC0

ADC1

DMA0CTH

DMA0CTL

Repeat Counter Limit

DMA0DSH

DMA0DSL

Current XRAM Address

DMA0DAH

DMA0DAL

Beginning XRAM Address

DMA0CSH

DMA0CSL

Current Repeat Counter Value

6.1. Writing to the Instruction Buffer

The Instruction Buffer has 64 8-bit locations that can be programmed with a sequence of DMA instructions.

Filling the Instruction Buffer is done with the Special Function Registers DMA0IPT (DMA Instruction Write

Address Register, Figure 6.6) and DMA0IDT (DMA Instruction Write Data Register, Figure 6.7). Instruc-

tions are written to the Instruction Buffer at address DMA0IPT when the instruction word is written to

DMA0IDT. Reading the register DMA0IDT will return the instruction word at location DMA0IPT. After a write

or read operation on DMA0IDT, the DMA0IPT register is automatically incremented to the next Instruction

Buffer location.

Rev. 1.2

75

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