C8051F317 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F317

8/16 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F310/1/2/3/4/5/6/7

5.3.2. Tracking Modes

According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con-

verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.

In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When

the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion

is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR

signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low;

conversion begins on the rising edge of CNVSTR (see Figure 5.4). Tracking can also be disabled (shut-

down) when the device is in low power standby or sleep modes. Low-power track-and-hold mode is also

useful when AMUX settings are frequently changed, due to the settling time requirements described in

Section “5.3.3. Settling Time Requirements” on page 54.

CNVSTR

(AD0CM[2:0]=100)

SAR Clocks

A. ADC0 Timing for External Trigger Source

1 2 3 4 5 6 7 8 9 10 11

AD0TM=1

Low Power

or Convert

Track

Convert

Low Power

Mode

AD0TM=0

Track or Convert

Convert

Track

Write '1' to AD0BUSY,

Timer 0, Timer 2,

Timer 1, Timer 3 Overflow

(AD0CM[2:0]=000, 001,010

011, 101)

SAR Clocks

AD0TM=1

B. ADC0 Timing for Internal Trigger Source

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Low Power

or Convert

Track

Convert

Low Power Mode

SAR Clocks

AD0TM=0

1 2 3 4 5 6 7 8 9 10 11

Track or

Convert

Convert

Track

Figure 5.4. 10-Bit ADC Track and Conversion Example Timing

Rev. 1.6

53

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