C8051F342 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F342

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

Bit

MASTER

TXMODE

STA

STO

ACKRQ

ARBLOST

ACK

SI

Table 17.3. Sources for Hardware Changes to SMB0CN

Set by Hardware When:

Cleared by Hardware When:

• A START is generated.

• A STOP is generated.

• Arbitration is lost.

• START is generated.

• A START is detected.

• SMB0DAT is written before the start of an

• Arbitration is lost.

SMBus frame.

• SMB0DAT is not written before the

start of an SMBus frame.

• A START followed by an address byte is

• Must be cleared by software.

received.

• A STOP is detected while addressed as a • A pending STOP is generated.

slave.

• Arbitration is lost due to a detected STOP.

• A byte has been received and an ACK

• After each ACK cycle.

response value is needed.

• A repeated START is detected as a MASTER • Each time SI is cleared.

when STA is low (unwanted repeated START).

• SCL is sensed low while attempting to gener-

ate a STOP or repeated START condition.

• SDA is sensed low while transmitting a ‘1’

(excluding ACK bits).

• The incoming ACK value is low (ACKNOWL- • The incoming ACK value is high (NOT

EDGE).

ACKNOWLEDGE).

• A START has been generated.

• Must be cleared by software.

• Lost arbitration.

• A byte has been transmitted and an ACK/

NACK received.

• A byte has been received.

• A START or repeated START followed by a

slave address + R/W has been received.

• A STOP has been received.

Rev. 1.3

197

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