C8051F342 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F342

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D

Table 20.1. SPI Slave Timing Parameters

Parameter

TMCKH

TMCKL

TMIS

TMIH

TSE

TSD

TSEZ

TSDZ

TCKH

TCKL

TSIS

TSIH

TSOH

TSLH

Description

Min

Max

Units

Master Mode Timing* (See Figure 20.8 and Figure 20.9)

SCK High Time

1 x TSYSCLK

ns

SCK Low Time

MISO Valid to SCK Shift Edge

1 x TSYSCLK

ns

1 x TSYSCLK + 20

ns

SCK Shift Edge to MISO Change

0

ns

Slave Mode Timing* (See Figure 20.10 and Figure 20.11)

NSS Falling to First SCK Edge

2 x TSYSCLK

ns

Last SCK Edge to NSS Rising

2 x TSYSCLK

ns

NSS Falling to MISO Valid

4 x TSYSCLK ns

NSS Rising to MISO High-Z

SCK High Time

5 x TSYSCLK

4 x TSYSCLK ns

ns

SCK Low Time

5 x TSYSCLK

ns

MOSI Valid to SCK Sample Edge

2 x TSYSCLK

ns

SCK Sample Edge to MOSI Change

2 x TSYSCLK

ns

SCK Shift Edge to MISO Change

4 x TSYSCLK ns

Last SCK Edge to MISO Change (CKPHA = 1

ONLY)

6 x TSYSCLK 8 x TSYSCLK ns

*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).

234

Rev. 1.3

Share Link: