C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

17. Reset Sources

Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this

reset state, the following occur:

 CIP-51 halts program execution

 Special Function Registers (SFRs) are initialized to their defined reset values

 External Port pins are forced to a known state

 Interrupts and timers are disabled.

All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal

data memory are unaffected during a reset; any previously stored data is preserved. However, since the

stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.

The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled

during and after the reset. For VDD Monitor and power-on resets, the RST pin is driven low until the device

exits the reset state.

On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-

nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-

gram execution begins at location 0x0000.

Px.x

Px.x

Comparator 0

+

-

C0RSEF

VDD

Supply

Monitor

+

-

Enable

Power On

Reset

0

(wired-OR)

RST

XTAL1

XTAL2

Low

Frequency

Oscillator

Internal

Oscillator

External

Oscillator

Drive

Missing

Clock

Detector

(one-

shot)

EN

PCA

WDT

EN

System

Clock

Clock Select

CIP-51

Microcontroller System Reset

Core

Extended Interrupt

Handler

(Software Reset)

SWRSF

Reset

Funnel

Errant Flash

Operation

Figure 17.1. Reset Sources

Rev. 1.4

129

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