C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F38B-GMR Datasheet PDF : 321 Pages
| |||
C8051F380/1/2/3/4/5/6/7/C
SFR Definition 20.16. P3: Port 3
Bit
7
6
5
4
3
2
1
0
Name
P3[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xB0; SFR Page = All Pages; Bit Addressable
Bit Name
Description
Write
7:0 P3[7:0] Port 3 Data.
0: Set output latch to logic
Sets the Port latch logic
LOW.
value or reads the Port pin 1: Set output latch to logic
logic state in Port cells con- HIGH.
figured for digital I/O.
Read
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
SFR Definition 20.17. P3MDIN: Port 3 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF4; SFR Page = All Pages
Bit
Name
Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
168
Rev. 1.4
Share Link: 