C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

USB Register Definition 21.20. EINCSRL: USB0 IN Endpoint Control Low

Bit

7

6

5

4

3

2

1

0

Name

CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY

Type

R

W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

USB Register Address = 0x11

Bit Name

Description

Write

Read

7 Unused Read = 0b. Write = don’t care.

6 CLRDT Clear Data Toggle Bit. Software should write 1 to This bit always reads 0.

this bit to reset the IN End-

point data toggle to 0.

5 STSTL Sent Stall Bit.

Hardware sets this bit to 1 when a STALL handshake signal is transmitted. The FIFO is

flushed, and the INPRDY bit cleared. This flag must be cleared by software.

4 SDSTL Send Stall.

Software should write 1 to this bit to generate a STALL handshake in response to an IN

token. Software should write 0 to this bit to terminate the STALL signal. This bit has no

effect in ISO mode.

3 FLUSH FIFO Flush Bit.

Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint

FIFO. The FIFO pointer is reset and the INPRDY bit is cleared. If the FIFO contains mul-

tiple packets, software must write 1 to FLUSH for each packet. Hardware resets the

FLUSH bit to 0 when the FIFO flush is complete.

2 UNDRUN Data Underrun Bit.

The function of this bit depends on the IN Endpoint mode:

ISO: Set when a zero-length packet is sent after an IN token is received while bit

INPRDY = 0.

Interrupt/Bulk: Set when a NAK is returned in response to an IN token.

This bit must be cleared by software.

1 FIFONE FIFO Not Empty.

0: The IN Endpoint FIFO is empty.

1. The IN Endpoint FIFO contains one or more packets.

0 INPRDY In Packet Ready.

Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO.

Hardware clears INPRDY due to any of the following: 1) A data packet is transmitted. 2)

Double buffering is enabled (DBIEN = 1) and there is an open FIFO packet slot. 3) If the

endpoint is in Isochronous Mode (ISO = 1) and ISOUD = 1, INPRDY will read 0 until the

next SOF is received.

Note: An interrupt (if enabled) will be generated when hardware clears INPRDY as a result of a

packet being transmitted.

Rev. 1.4

199

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