C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

Figure 3.3. TQFP-48 Recommended PCB Land Pattern

Table 3.3. TQFP-48 PCB Land Pattern Dimensions

Dimension

C1

C2

E

X1

Y1

Min

Max

8.30

8.40

8.30

8.40

0.50 BSC

0.20

0.30

1.40

1.50

Notes:

General:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design:

3. All metal pads are to be non-solder mask defined (NSMD). Clearance between

the solder mask and the metal pad is to be 60 µm minimum, all the way around

the pad.

Stencil Design:

4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

5. The stencil thickness should be 0.125 mm (5 mils).

6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.

Card Assembly:

7. A No-Clean, Type-3 solder paste is recommended.

8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Rev. 1.4

27

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