C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
Manufacturer
C8051F38B-GMR Datasheet PDF : 321 Pages
| |||
C8051F380/1/2/3/4/5/6/7/C
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +85 °C, 25 MHz system clock unless otherwise specified.
Parameter
Digital Supply Voltage1
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)2
Specified Operating
Temperature Range
Test Condition
Min Typ
VRST1 3.3
— 1.5
Max
3.6
—
Unit
V
V
0
— 48 MHz
–40 — +85 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD3
SYSCLK = 48 MHz, VDD = 3.3 V
— 12 14 mA
SYSCLK = 24 MHz, VDD = 3.3 V
—
7
8
mA
SYSCLK = 1 MHz, VDD = 3.3 V
— 0.45 0.85 mA
SYSCLK = 80 kHz, VDD = 3.3 V
— 280 — µA
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
Idle IDD3
SYSCLK = 48 MHz, VDD = 3.3 V
SYSCLK = 24 MHz, VDD = 3.3 V
SYSCLK = 1 MHz, VDD = 3.3 V
—
6.5
8
mA
—
3.5
5
mA
— 0.35 — mA
SYSCLK = 80 kHz, VDD = 3.3 V
— 220 — µA
Digital Supply Current
Oscillator not running (STOP mode),
—
1
— µA
(Stop or Suspend Mode, shut- Internal Regulators OFF, VDD = 3.3 V
down)
Oscillator not running (STOP or SUS-
— 100 —
µA
PEND mode), REG0 and REG1 both in
low power mode, VDD = 3.3 V.
Oscillator not running (STOP or SUS-
— 150 —
µA
PEND mode), REG0 OFF, VDD = 3.3 V.
Digital Supply Current for USB
Module
(USB Active Mode4)
USB Clock = 48 MHz, VDD = 3.3 V
—
8
— mA
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Includes normal mode bias current for REG0 and REG1. Does not include current from internal oscillators,
USB, or other analog peripherals.
4. An additional 220uA is sourced by the D+ or D- pull-up to the USB bus when the USB pull-up is active.
38
Rev. 1.4
Share Link: 