C8051F38B-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F38B-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

9. Voltage Regulators (REG0 and REG1)

C8051F380/1/2/3/4/5/6/7/C devices include two internal voltage regulators: one regulates a voltage source

on REGIN to 3.3 V (REG0), and the other regulates the internal core supply to 1.8 V from a VDD supply of

1.8 to 3.6 V (REG1). When enabled, the REG0 output appears on the VDD pin and can be used to power

external devices. REG0 can be enabled/disabled by software using bit REG0DIS in register REG01CN

(SFR Definition 9.1). REG1 has two power-saving modes built into the regulator to help reduce current

consumption in low-power applications. These modes are accessed through the REG01CN register. Elec-

trical characteristics for the on-chip regulators are specified in Table 5.5 on page 40.

Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.

The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powered

function. REG0 configuration options are shown in “4. Typical Connection Diagrams” Figure 4.1–

Figure 4.4.

9.1. Voltage Regulator (REG0)

See “4. Typical Connection Diagrams” for typical connection diagrams using the REG0 voltage regulator.

9.1.1. Regulator Mode Selection

REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power

mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is

degraded. See Table 5.5 for normal and low power mode supply current specifications. The REG0 mode

selection is controlled via the REG0MD bit in register REG01CN.

9.1.2. VBUS Detection

When the USB Function Controller is used (see section Section “21. Universal Serial Bus Controller

(USB0)” on page 172), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register

REG01CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be gener-

ated when the VBUS signal has either a falling or rising edge. The VBUS interrupt is edge-sensitive, and

has no associated interrupt pending flag. See Table 5.5 for VBUS input parameters.

Important Note: When USB is selected as a reset source, a system reset will be generated when a falling

or rising edge occurs on the VBUS pin. See Section “17. Reset Sources” on page 129 for details on select-

ing USB as a reset source.

9.2. Voltage Regulator (REG1)

Under default conditions, the internal REG1 regulator will remain on when the device enters STOP mode.

This allows any enabled reset source to generate a reset for the device and bring the device out of STOP

mode. For additional power savings, the STOPCF bit can be used to shut down the regulator and the inter-

nal power network of the device when the part enters STOP mode. When STOPCF is set to 1, the RST pin

and a full power cycle of the device are the only methods of generating a reset.

REG1 offers an additional low power mode intended for use when the device is in suspend mode. This low

power mode should not be used during normal operation or if the REG0 Voltage Regulator is disabled. See

Table 5.5 for normal and low power mode supply current specifications. The REG1 mode selection is con-

trolled via the REG1MD bit in register REG01CN.

Important Note: At least 12 clock instructions must occur after placing REG1 in low power mode before

the Internal High Frequency Oscillator is Suspended (OSCICN.5 = 1b).

74

Rev. 1.4

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