C8051F911-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F911-GM

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

11.1. SFR Paging

To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been

implemented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in

Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.

Table 11.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,

including the SFRPAGE register. SFRs only accessible from Page 0xF are in bold. SFRs only available on

the ‘F912 and ‘F902 devices are in blue.

The following procedure should be used when accessing SFRs on Page 0xF:

1. Save the current interrupt state (EA_save = EA).

2. Disable Interrupts (EA = 0).

3. Set SFRPAGE = 0xF.

4. Access the SFRs located on SFR Page 0xF.

5. Set SFRPAGE = 0x0.

6. Restore interrupt state (EA = EA_save).

Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)

F8

F0 B

E8

E0 ACC

D8

D0 PSW

C8

C0

B8

IREF0CF ADC0PWR

B0

A8 IE

CLKSEL

A0 P2

98

90 P1 CRC0DAT CRC0CN

88

80 P0

SP

DPL

0(8)

1(9)

2(A)

(bit addressable)

CRC0IN

DPH

3(B)

P0DRV

DC0MD

4(C)

FLWR

EIP1

EIE1

EIP2

EIE2

ADC0TK

PMU0MD

P1DRV

P2DRV SFRPAGE

CRC0FLIP CRC0AUTO CRC0CNT

TOFFL

5(D)

TOFFH

6(E)

PCON

7(F)

114

Rev. 1.0

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