C8051F91x-C8051F90x
Table 12.1. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Pending Flag
Enable Flag
Priority
Control
Reset
0x0000 Top None
N/A N/A
Always
Enabled
Always
Highest
External Interrupt 0 (INT0) 0x0003 0 IE0 (TCON.1)
Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow
0x000B 1 TF0 (TCON.5)
Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (INT1) 0x0013 2 IE1 (TCON.3)
Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow
UART0
0x001B
0x0023
3 TF1 (TCON.7)
4
RI0 (SCON0.0)
TI0 (SCON0.1)
Y Y ET1 (IE.3) PT1 (IP.3)
Y N ES0 (IE.4) PS0 (IP.4)
Timer 2 Overflow
SPI0
0x002B
0x0033
5
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
6
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
Y N ET2 (IE.5) PT2 (IP.5)
Y N ESPI0 (IE.6) PSPI0 (IP.6)
SMB0
0x003B 7 SI (SMB0CN.0)
YN
ESMB0
(EIE1.0)
PSMB0
(EIP1.0)
SmaRTClock Alarm
0x0043
ADC0 Window Comparator 0x004B
ADC0 End of Conversion
Programmable Counter
Array
Comparator0
0x0053
0x005B
0x0063
Comparator1
0x006B
Timer 3 Overflow
0x0073
8 ALRM (RTC0CN.2)2
9 AD0WINT (ADC0CN.3)
10 AD0INT (ADC0STA.5)
11
CF (PCA0CN.7)
CCFn (PCA0CN.n)
12
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
13
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
14
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
NN
EARTC0
(EIE1.1)
PARTC0
(EIP1.1)
Y
N
EWADC0
(EIE1.2)
PWADC0
(EIP1.2)
YN
EADC0
(EIE1.3)
PADC0
(EIP1.3)
YN
EPCA0
(EIE1.4)
PPCA0
(EIP1.4)
NN
ECP0
(EIE1.5)
PCP0
(EIP1.5)
NN
ECP1
(EIE1.6)
PCP1
(EIP1.6)
NN
ET3
(EIE1.7)
PT3
(EIP1.7)
Supply Monitor Early
Warning
0x007B
15
VDDOK (VDM0CN.5)1
VBATOK (VDM0CN.4)1, 3
EWARN
(EIE2.0)
PWARN
(EIP2.0)
Port Match
0x0083
SmaRTClock Oscillator Fail 0x008B
SPI1
0x0093
16 None
17 OSCFAIL (RTC0CN.5)2
SPIF (SPI1CN.7)
18
WCOL (SPI1CN.6)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
NN
NN
EMAT
(EIE2.1)
ERTC0F
(EIE2.2)
ESPI1
(EIE2.3)
PMAT
(EIP2.1)
PFRTC0F
(EIP2.2)
PSPI1
(EIP2.3)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
3. 8Blue text Indicates a bit only available on ‘F912 and ‘F902 devices.
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Rev. 1.0