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C8051F989-GM View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
Manufacturer
C8051F989-GM Datasheet PDF : 322 Pages
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C8051F99x-C8051F98x
15.1. Normal Mode
The MCU is fully functional in normal mode. Figure 15.1 shows the on-chip power distribution to various
peripherals. There are two supply voltages powering various sections of the chip: VDD and the 1.8 V inter-
nal core supply. All analog peripherals are directly powered from the VDD pin. All digital peripherals and the
CIP-51 core are powered from the 1.8 V internal core supply. RAM, PMU0 and the SmaRTClock are
always powered directly from the VBAT pin in sleep mode and powered from the core supply in all other
power modes.
VDD
1.8 to 3.6 V
Sleep
PMU0
SmaRTClock
GPIO
Analog Peripherals
VREG0
Active/Idle/
Stop/Suspend 1.8 V
RAM
VREF
IREF0
A
M
U
ADC
+
X
TEMP
SENSOR
-
VOLTAGE
COMPARATOR
Digital Peripherals
CIP-51
Core
Flash
UART
SPI
Timers
SMBus
Figure 15.1. C8051F99x-C8051F98x Power Distribution
162
Rev. 1.0

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