CDB42406 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB42406 Datasheet PDF : 32 Pages
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CDB42406
JUMPER /
SWITCH
S/PDIF In
Setup (S1)
S/PDIF In
Setup (S1)
J3
PURPOSE
IDENTIFIER
Optical or Coaxial S/PDIF
-
Input Select
I2S or Left Justified
-
Input Select
Selects source of voltage
-
for the VD supply
J5
Selects source of voltage
-
for the VLS and VLC sup-
plies
J6
Selects source of voltage
-
for the VA supply
DAC SETUP DAC Speed Mode Select DAC_Mx
(S2)
DAC SETUP Interface Format Select
(S2)
DIFx
DAC SETUP
(S2)
Resets DAC
ADC SETUP ADC Speed Mode Select
(S3)
RST_DAC
ADC_Mx
ADC SETUP MCLK/LRCK Ratio Select
(S3)
384x/256x
ADC SETUP ADC and CS8406 Inter-
(S3)
face Format Selection
I2S/LJ
ADC SETUP
(S3)
Powerdown ADC
PDN_ADC
J9, J12, J14, Mute Circuit Connection
-
J17, J20, J23
POSITION
*OPTICAL
COAXIAL
*LJ
I2S
VD_IN
+3.3V
*+5V
+3.3V
*+5V
VA_IN
+3.3V
*+5V
*00
01
10
11
*00
01
10
11
0
*1
00
01
10
*11
*0
1
0
*1
0
*1
*Shunted
Open
FUNCTION SELECTED
Optical Input
Coaxial Input
Left Justified S/PDIF Input
I2S S/PDIF Input
Voltage source is J4 binding post
Voltage source is +3.3 V regulator
Voltage source is +5 V regulator
Voltage source is +3.3 V regulator
Voltage source is +5 V binding post (J1)
Voltage source is J7 binding post
Voltage source is +3.3 V regulator
Voltage source is +5 V binding post (J1)
Single-Speed Mode, w/out De-emphasis
Single-Speed Mode, with De-emphasis
Double-Speed Mode
Quad-Speed Mode
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified 16-bit data
Right Justified 24-bit data
DAC reset is enabled
DAC reset is disabled
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Clock Master, Quad-Speed Mode
Clock Slave, All Speed Modes
MCLK/LRCK ratio is 256
MCLK/LRCK ratio is 384
Left Justified, up to 24-bit data
I2S, up to 24-bit data
ADC is powered down
ADC is powered up
Connects Mute Circuit to AOUTxx
Disconnects Mute Circuit from AOUTxx
*Default factory settings
Table 2. Jumper/Switch Settings
18
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