CS4216-KL View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS4216-KL

16-Bit Stereo Audio Codec

Cirrus Logic 

CS4216

Miscellaneous

RESET - Reset Input, PIN 2.(L), 40(Q).

Resets the CS4216 into a known state, and must be initiated after power-up or power-down

mode. Releasing RESET caused the CS4216 to initiate a calibration sequence. RESET should

also be initiated when changing sample frequencies in any master sub-mode.

CLKIN - Master Clock, PIN 3(L), 41(Q).

CLKIN is the master clock that operates the internal logic. In serial mode 1,

CLKIN = 512×hFs, where hFs is the highest sample frequency needed. Different sample

frequencies are obtained by changing the ratio of SCLK to CLKIN. In serial mode 2, CLKIN is

not used and must be tied low. In serial modes 3 and 4, CLKIN is 256×hFs, where different

sample frequencies are obtained by either changing the ratio of SCLK to CLKIN in slave mode,

or changing the format pin values (F2-F0) in master mode.

PDN - Power Down, PIN 13(L), 7(Q).

This pin, when low, causes the CS4216 to go into a power down state. RESET should be held

low for 50 ms when exiting the power down state to allow time for the voltage reference to

settle.

DI1 - Parallel Digital Bit Input #1, PIN 33(L), 27(Q).

This pin value is reflected in the DI1 bit in the sub-frame.

DO1 - Parallel Digital Bit Output #1, PIN 37(L), 31(Q).

This pin reflects the value of the DO1 bit in the sub-frame.

NC - No Connection,

PINS 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 19(L)

PINS 44, 1, 2, 3, 4, 5, 6, 8, 11, 12, 13(Q).

These pins should be left floating with no trace attached to allow backwards compatibility with

future revisions. They should not be used as a convenient path for signal traces.

DS83F2

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