CS42324 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS42324

10-In, 6-Out, 2 Vrms Audio CODEC

Cirrus Logic 

CS42324

6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM)

This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the

DAC2_AMUTEL interrupt is unmasked, meaning that if the DAC2_AMUTEL condition occurs, the INT pin

will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on

page 59. If the DAC2_AMUTELM bit is set, the DAC2_AMUTEL condition is masked, meaning that its oc-

currence will not affect the INT pin.

6.19.2 DAC2 Auto Mute Right Mask (DAC2_AMUTERM)

This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the

DAC2_AMUTER interrupt is unmasked, meaning that if the DAC2_AMUTER condition occurs, the INT pin

will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on

page 59. If the DAC2_AMUTERM bit is set, the DAC2_AMUTER condition is masked, meaning that its

occurrence will not affect the INT pin.

6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM)

This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the

DAC1_AMUTEL interrupt is unmasked, meaning that if the DAC1_AMUTEL condition occurs, the INT pin

will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on

page 59. If the DAC1_AMUTELM bit is set, the DAC1_AMUTEL condition is masked, meaning that its oc-

currence will not affect the INT pin.

6.19.4 DAC1 Auto Mute Right Mask (DAC1_AMUTELM)

This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the

DAC1_AMUTER interrupt is unmasked, meaning that if the DAC1_AMUTER condition occurs, the INT pin

will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on

page 59. If the DAC1_AMUTERM bit is set, the DAC1_AMUTER condition is masked, meaning that its

occurrence will not affect the INT pin.

6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM)

This bit serves as a mask for the serial port 2 clock error interrupt source. If this bit is cleared, the

SP2_CLKERR interrupt is unmasked, meaning that if the SP2_CLKERR bit is set, the INT pin will go ac-

tive according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If

the SP2_CLKERRM bit is set, the SP2_CLKERR condition is masked, meaning that its occurrence will

not affect the INT pin.

6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM)

This bit serves as a mask for the serial port 1 clock error interrupt source. If this bit is cleared, the

SP1_CLKERR interrupt is unmasked, meaning that if the SP1_CLKERR bit is set, the INT pin will go ac-

tive according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If

the SP1_CLKERRM bit is set, the SP1_CLKERR condition is masked, meaning that its occurrence will

not affect the INT pin.

60

DS721A6

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