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CS4365-CQZ(2005) View Datasheet(PDF) - Cirrus Logic

Part Name
Description
Manufacturer
CS4365-CQZ
(Rev.:2005)
Cirrus-Logic
Cirrus Logic 
CS4365-CQZ Datasheet PDF : 51 Pages
First Prev 41 42 43 44 45 46 47 48 49 50
5.13 PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
CS4365
0
Reserved
0
5.13.1 Master Clock DIVIDE by 2 ENABLE (mclkdiv)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
44
DS670PP1

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