CS44600
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(VD = 2.5 V, VDP = VLS = 3.3 V; VLC = 2.5 V to 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol Min Typ Max Units
CCLK Clock Frequency
CS High Time between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
fsck
0
-
6.0
MHz
tcsh
1.0
-
-
µs
tcss
20
-
-
ns
tscl
66
-
-
ns
tsch
66
-
-
ns
tdsu
40
-
-
ns
(Note 19)
tdh
15
-
-
ns
tpd
-
-
50
ns
tr1
-
-
25
ns
tf1
-
-
25
ns
(Note 20)
tr2
-
-
100
ns
(Note 20)
tf2
-
-
100
ns
19. Data must be held for sufficient time to bridge the transition time of CCLK.
20. For fsck <1 MHz.
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
CDOUT
t dsu
t dh
t pd
Figure 9. Control Port Timing - SPI Format
DS633F1
15