CRD44800-ST-FB View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CRD44800-ST-FB Datasheet PDF : 76 Pages
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CS44600
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
Attack Rate - 384 kHz
(µs per 1/8 dB)
83.33
4.167
2.083
1.389
0.926
Attack Rate - 421.875 kHz
(µs per 1/8 dB)
75.852
3.793
1.896
1.264
0.843
Table 10. Limiter Attack Rate Settings
7.17 Limiter Release Rate (address 17h)
7
RRATE7
6
RRATE6
5
RRATE5
4
RRATE4
3
RRATE3
2
RRATE2
1
RRATE1
0
RRATE0
7.17.1 Release Rate (RRATE[7:0])
Default = 00100000
Function:
The limiter release rate is user selectable. The effective rate is a function of the SRC output sampling fre-
quency and the value in the Release Rate register. Rates are calculated using the function
RATE = (512/{value})/SRC Fs, where {value} is the decimal value in the Release Rate register and SRC
Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency. SRC
Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note: A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see Peak Limiter Control Register (address 15h)).
Binary Code
00000001
00010100
00101000
00111100
01011010
Decimal Value
1
20
40
60
90
Release Rate - 384 kHz
(µs per 1/8 dB)
1333.333
66.667
33.333
22.222
14.815
Release Rate - 421.875 kHz
(µs per 1/8 dB)
1213.630
60.681
30.341
20.227
13.485
Table 11. Limiter Release Rate Settings
7.18 Chnl XX Load Compensation Filter - Coarse Adjust
(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
7
RESERVED
6
5
4
3
2
1
0
RESERVED CHXX_CORS5 CHXX_CORS4 CHXX_CORS3 CHXX_CORS2 CHXX_CORS1 CHXX_CORS0
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0])
Default = 000000
Function:
The Channel Load Compensation Filter Coarse Adjustment settings control the amount of attenuation of
this single-pole filter and are used in conjunction with the Fine Adjustment bits to compensate for speaker
impedance load variations. Each PWM channel is controlled by an associated register. The coarse ad-
justment bits will attenuate the audio response curve according to the table below in 0.1 dB increments.
Filter setting values less than -4.0 dB will cause the PWM output to mute.
60
DS633F1
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