CS4952 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS4952

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4952/53

OPERATIONAL DESCRIPTION

Reset Hierarchy

The CS4952/3 is equipped with an active low asyn-

chronous reset input pin RESET. RESET is used to

initialize the internal registers and the internal state

machines for subsequent default operation. See the

electrical and timing specification section of this

data sheet for specific CS4952/3 chip reset and

power-on signaling timing requirements and re-

strictions. All chip outputs are valid after a time pe-

riod following RESET pin low.

When the RESET pin is held low, the host interface

in the CS4952/3 is disabled and will not respond to

host initiated bus cycles.

A reset initializes the CS4952/3 internal registers to

their default values as described by Table 5. In the

default state, the CS4952/53 video DACs are dis-

abled and the device is configured to internally pro-

vide blue field video data to the DACs (any input

data present on the V [7:0] pins is ignored). Other-

wise the CS4952/53 registers are configured for

NTSC-M CCIR601 output operation. At a mini-

mum, the DAC register (0x04) must be written (to

enable the DACs) and the IN_MODE bit of the

CONTROL_0 register (0x01) must be set (to en-

able CCIR601 data input on V [7:0]) for the

CS4952/53 to become operational after RESET.

Video Timing

Slave Mode Input Interface

In Slave Mode, the CS4952/3 takes VSYNC and

HSYNC as inputs. Slave Mode is the default fol-

lowing a reset and is changed to Master Mode via a

contol register bit (CONTROL_0 [4]). The

CS4952/3 is limited to CCIR601 horizontal and

vertical input timing. All clocking in the CS4952/3

is generated from the CLK pin. In Slave Mode the

Sync Generator uses externally provided horizontal

and vertical sync signals to synchronize the internal

timing of the CS4952/3.

Video data that is sent to the CS4952/3 must be

synchronized to the horizontal and vertical sync

signals. Figure 6 illustrates horizontal timing for

CCIR601 input in Slave Mode. Note that the

CS4952/3 expects to receive the first active pixel

data on clock cycle 245 (NTSC) when bit

SYNC_DLY=0 in the CONTROL_2 Register

(Ox02). When SYNC_DLY=1, it expects the first

active pixel data on clock cycle 246 (NTSC).

Master Mode Input Interface

The CS4952/3 defaults to Slave Mode following

RESET high but may be switched into Master

Mode via the MSTR bit in the CONTROL_0 Reg-

ister (0x00). In Master Mode, the CS4952/3 uses

the VSYNC, HSYNC and FIELD device pins as

NTSC 27MHz Clock Count 1682 1683 1684 1685 1686 • • • 1716 1 2 3 • • • 128 129 • • • 244 245 246 247 248

PAL 27MHz Clock Count 1702 1703 1704 1705 1706 • • • 1728 1 2 3 • • • 128 129 • • • 264 265 266 267 268

CLK

HSYNC* (input)

V[7:0] Y

(SYNC_DLY=0)

•••

Cr Y

active pixel

#720

horizontal blanking

V[7:0] Cb Y

(SYNC_DLY=1)

active pixel

#719

Cr Y

active pixel

#720

horizontal blanking

Figure 6. CCIR601 Input Slave Mode Horizontal Timing

Cb Y Cr Y

active pixel active pixel

#1

#2

Cb Y Cr

active pixel active pixel

#1

#2

14

DS223PP2

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