CS485xx Family Data Sheet
32-bit Audio Decoder DSP Family
10. Revision History
Revision
Date
Changes
A1
JUL 2006
Advance release.
A2
JUL 2006
Updated pinout definition for pins 26 and 27. Updated typical power
numbers.
A3
DEC 5 2006
Updated sections 2.0, 4.2.1, 5.8, Table 3, Table 4, to show new device
numbering scheme. Updated sections 8.1, 8.2, 8.3.
PP1
MAR 12 2007
Preliminary Release
Changed title of data sheet from CS48500 Data Sheet to CS485xx Fam-
PP2
F1
F2
December 18, 2007
April 21, 2007
July 14, 2008
ily Data Sheet to cover all CS485xx family products. Updated Standby
Power specification in Section . Updated DAO timing specifications and
T timing diagrams in Section 5.15.
Removed DSD Phase Modulation Mode from Section 5.14. Removed
F reference to MCLK in Section 5.14. Redefined Master mode clock
speed for SCP_CLK in Section 5.10. Redefined DC leakage character-
ization data in Section 5.3. Added typical crystal frequency values in
A Table Footnote 1 under Section 5.7. Modified Footnote 1 under Section
5.9. Modified power supply characteristics in Section 5.4,
R Added reference to support for time division multiplexed (TDM) one-line
D data mode for DAO port in Section 4.2.2.
CONFIDENTDIEALLPHI
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©Copyright 2008 Cirrus Logic, Inc.
DS734F2
CONFIDENTIAL