CS61310(2003) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS61310
(Rev.:2003)

T1 Line Interface Unit

Cirrus Logic 

CS61310

RRDATA - Received Data, Pin 7.

Unipolar data (single-line NRZ) data is output on RDATA when pin 4, TNEG/UBS, is held high.

RCLK - Recovered Clock Output, Pin 8.

RCLK outputs the clock recovered from the input signal at RTIP and RRING. In a Loss of Signal state

RCLK is driven either by MCLK or the crystal oscillator, or retains the frequency prior to the LOS state,

depending on the clocks provided. While LOS is true, RCLK will be driven either by MCLK or the crystal

oscillator. If the jitter attenuator is in the receive path, RCLK will make a smooth transition to the LOS

timing. RCLK will remain at its frequency prior to LOS.

RTIP,RRING - Receive Tip, Receive Ring, Pins 19,20.

The B8ZS signal received from the line is input via these pins. A 1:1 transformer and appropriate

matching resistors are required as shown in the applications section. Data and clock recovered from the

signal input on these pins is output via RPOS, RNEG, and RCLK.

TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13,16

These pins are the output of the differential transmit driver. The transformer and matching resistors can

be chosen to give the desired pulse height (see Application Schematics)

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DS440F1 FEB ‘03

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