CS8900A-CQZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS8900A-CQZ

Crystal LAN™ Ethernet Controller

Cirrus Logic 

CS8900A

Crystal LAN™ Ethernet Controller

Pin Name Pin #

DMACK1

14

DMACK0

16

SD08-SD15 27-24, 21-18

MEMW

28

MEMR

29

Pin Name

IOR

IOW

SD0 - SD7

RESET

SLEEP

Pin #

61

62

65-68, 71-74

75

77

Table 41. (continued)

The input pins not included in this test are:

Pin Name

AEN

TEST

Dl+

Dl-

Cl+

Pin #

63

76

79

80

81

Pin Name

Cl-

RXD+

RXD-

XTAL1

Pin #

82

91

92

97

Table 42.

After the Input Cycle is complete, one more cy-

cle of AEN returns all digital output pins and bi-

directional pins to a high-impedance state.

6.2.3 Continuity Cycle

The combination of a complete Output Cycle,

a complete Input Cycle, and an additional AEN

cycle is called a Continuity Cycle. Each Conti-

nuity Cycle lasts for 85 AEN clock cycles. The

first Continuity Cycle can be followed by addi-

tional Continuity Cycles by keeping TEST low

and continuing to cycle AEN. When TEST is

driven high, the CS8900A exits Boundary

Scan mode and AEN is again used as the ISA-

bus Address Enable.

Figure 32 shows a complete Boundary Scan

Continuity Cycle.

Figure 33 shows Boundary Scan timing.

CIRRUS LOGIC PRODUCT DATASHEET

DS271F4

109

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